The P6600 is said to build on the 32bit P5600 and to pave the way to higher performance 64bit MIPS processors. Meanwhile, the M6200 and M6250 broaden the M-class roadmap, addressing deeply embedded designs which require higher performance and larger address space.
Tony King-Smith, pictured, executive vp of marketing, said: “Customers keep telling us they want different price/performance CPU cores to what is currently on offer in the market. Responding to their needs, we’re delivering a more comprehensive roadmap that addresses their real system needs and provides them with the choice of CPU IP cores they tell us they really want.”
The 64bit P6600 is based on a 16 stage multi issue out of order (OoO) pipeline implementation. It features 128bit MIPS SIMD architecture (MSA) support for parallel processing of vector operations and what the company calls sophisticated branch prediction, with a fully associative Level 1 branch target buffer and an improved Level 2 cache sub-system.
The low-power M6200 and 6250 are 32bit CPUs based on a six stage pipeline implementation. According to Imagination, the cores support 30% higher frequencies than the MIPS microAptiv CPU. Also featured is integrated DSP and SIMD functionality, as well as support for the microMIPS r6 Instruction Set Architecture.
The M6200 MCU features a memory controller for tightly coupled 64bit Instruction/Data SRAM and a memory protection unit. The M6250 has a memory controller for Instruction/Data L1 cache and, optionally, tightly coupled ScratchPad RAMs (SPRAMs). With 40bit physical addressing, the core also boasta a memory management unit.
King-Smith noted: “Our partners have announced multiple devices based on the latest MIPS Warrior CPUs and we are delighted to see MIPS based products reach the market as we continue to deliver new cores designed to deliver the power, performance and area our customers need in their products.”
