Despite apparent success in a number of sectors – and with licensing deals with a number of leading consumer electronics companies – MIPS started to cut employment in 2008 and was acquired by Imagination Technologies towards the end of 2012.
Having integrated MIPS' technology with its existing processor IP portfolio, Imagination created a new road map for the company, including new 32 and 64bit MIPS CPU cores.
Sir Hossein Yassaie, Imagination's CEO said in June 2013: "We have an outstanding range of cores and that will be complemented by our forthcoming 'Warrior' cores, which will provide levels of performance, efficiency and functionality that go beyond other offerings in the market."
Warrior cores, also known as the Series 5 generation, were said to include new architectural features and to offer 'best in class performance and efficiency' for a range of applications.
And Imagination took the opportunity to explain more about Series 5 at Embedded World in February.
Series 5 is an entry level range of CPU cores and initially comprises two cores: the M5100, with an integrated SRAM controller and real time execution unit, is optimised for low cost, low power microcontroller applications; and the M5150, featuring a high performance L1 cache controller and virtual memory management support for high performance embedded system applications (see fig 1).
According to the company, the M51xx cores are superset extensions of the MIPS microAptiv family of processor cores. They retain the five stage pipeline architecture and features such as the microMIPS instruction set architecture and power management features. The microMIPS instruction set blends optimised 16 and 32bit instructions, resulting in a reduction of code size of up to 30%, says the company.
Mark Throndson, Imagination's director of processor technology marketing, explained more. "It's been more than a year since MIPS was acquired by Imagination and during that time we've been putting a lot of effort into redesigning our product road map. At one end of the scale, we've introduced the P5600, a high end applications processor. At the other end, we've launched the M class of CPU cores." Throndson added the big thing that was being announced at Embedded World was that Imagination had taken virtualisation technology to the microcontroller level. "The motivation," he said, "is the Internet of Things; the need for security and reliability."
Virtualisation technology provides a secure partition within the MIPS architecture that allows for a multiple execution environment. "You can run multiple operating systems with partitions," Throndson continued, "or it could be an embedded system OS with secure aspects. Although you could use a secure coprocessor dedicated to running, for example, a digital rights management system, there's nothing like that available."
Imagination says the M class cores bring a new level of flexibility, security and reliability to entry level microcontroller based applications. Alongside these attributes, the cores are said to offer the highest CoreMark per MHz scores for microcontroller class devices, where CoreMark is a benchmark created by the Embedded Microprocessor Benchmark Consortium to allow an objective comparison of processor core performance.
Apart from application in the Internet of Things sector, Imagination says the Series 5 cores are suited to applications in sectors such as wireless communication, industrial control and automotive.
Tony King-Smith, Imagination's executive VP of marketing, said: "Imagination has seen the need for multiple execution domains right across the CPU spectrum, which is why we've rolled out virtualisation across our range of MIPS Series5 CPUs, including the entry level M51xx family."
The M51xx family has a number of common features. For example, both cores announced at Embedded World have five stage pipelines, with the processor offering 3.4 CoreMark/ MHz; a performance said to be equivalent to 1.57DMIPS/MHz.
There are 32 general registers and the cores feature a DSP and SIMD engine that executes more than 150 instructions, including 38 multiply and MAC operations. A floating point unit, optional for both cores, supports single and double precision and most instructions are said execute within one FPU cycle, with a four cycle latency.
Power consumption has been seen as an important parameter and Imagination claims that, when targeted at a 28nm HPM process, the M5150 core will run at up to 576MHz. Targeted at a 65nm low power process, the clock rate drops to 372MHz. For the M5100 core, the clock rates are 322MHz and 496MHz respectively. Both cores can be optimised for speed or area.
Ian Anderton, business development manager for MIPS processors, described the M51xx cores as coming from a long heritage, including the MIPS microAptiv architecture. "The M5100 is a flexible chip. It offers the user three cores in one – it can be the equivalent of a Cortex-M0, an M3 or an M4.
Essentially, the M5100 is microAptiv with virtualisation. It brings a 25% performance boost, plus double the DSP performance. Users will also get a 40% increase in floating point performance."
Throndson said the M51xx cores were scalable and aligned with the cost aspects of the embedded systems market. "Virtualisation is the hardware foundation which allows you to build security," he contended.
"Hypervisor technology takes advantage of hw virtualisation," he continued. "It runs at most privileged level, oversees partitioning process, ensuring there's no illegal activity."
Imagination suggests virtualisation could be useful in space constrained, low power systems, such as those aimed at the IoT or wearable devices. In a multiple guest environment, it says, one guest running a real time kernel could manage secure transmission of sensor data, while another guest, under RTOS control, could provide multimedia functionality.
Two virtualisation approaches are taken In the M5150, full virtualisation is provided using a root and guest transaction lookaside buffer MMU. But the M5100 provides what Imagination calls a 'lightweight' option, with virtualisation provided through root and guest fixed mapping translation (see fig 2).
MIPS has been undertaking work on the creation of anti tamper features for smart card processors and some of this work has been applied to the M51xx cores.
For applications that require higher levels of security, the M51xx cores include tamper resistant features that counter unwanted access to the processor's operating state.
"For example, we provide data and address scrambling," Throndson pointed out. "And we insert 'bubbles' into the pipeline to counter attempts to run power analysis techniques."
Bubbles, or random processor slips, disguise the timing and the power profile of an algorithm running on the processor. These bubbles make it more difficult to reverse engineer a design. Meanwhile, a secure debug feature prevents the core from being accessed and interrogated externally.
The RTL for the M51xx series was produced at the end of 2013 and the cores are now being designed in at a range of lead licensees, Throndson concluded.
