imec, Panasonic present 4K2K cmos image sensor

Based on a stagger laced dual exposure, the image sensor was processed using imec's 130nm cmos process on 200mm silicon wafers. The chip is a floating diffusion shared 4T pixel imager, with a pitch of 2.5microns and a conversion gain of 70µV/e-, which allows for both a classical rolling shutter or stagger laced scanning mode. The 4K2K 60fps imaging performance is realised by 12bit, column based delta-sigma a/d converters. The stagger laced scanning method is said to improve imaging sensitivity and realise a 50% reduction in output data rate by alternating the readout of two sets of horizontal pixel pairs arranged in two complementary checkerboard patterns. The overall power consumption of the imager is rated at less than 2W. "This is an important milestone for imec to demonstrate our capability to co-design, prototype and manufacture high performance cmos image sensors in our 200mm cmos fab," commented Rudi Cartuyvels, senior vp of smart systems and energy technologies at imec.