Intel unveils energy efficient network developments at ISSCC
Intel is presenting a paper to the International Solid State Circuits Conference (ISSCC) today that addresses energy efficient networks on chip (NoCs). It says NoCs are key enablers for exascale computation as they make it possible to shift the power budget away from communication and towards computation.
As core counts scale into the hundreds, on chip interconnect fabrics must support increasing heterogeneity and voltage/clock domains.
In its paper, Intel Labs describes a source synchronous 256 node NoC created on a 22nm Tri-Gate cmos process.
Featuring 'industry leading' energy efficiency, the NoC uses hybrid packet/circuit switching to create a bandwidth of 20.2Tbit/s.
Running from a 0.9V supply, the NoC is also said by Intel to be the first such circuit reported to operate at near threshold and ultra low voltages, reducing power consumption by a factor of nine to 363µW at 340mV.
