‘Record breaking’ processor designs to be presented at ISSCC

According to the event organiser, the papers include information on the highest frequency microprocessor yet developed, the highest number of x86 cores on one die, the highest energy efficiency and the most complex device ever developed. The IBM zEnterprise 196 server chip is said to be the fastest microrocessor yet. Running at 5.2GHz and fabricated using a 45nm cmos process, the device has four cores and 30Mbyte of cache memory, accounting in total for 1.4 billion transistors. The designers faced significant timing, power and noise problems in achieving the target performance. Meanwhile, the Intel Bangalore Westmere-EX integrates 10 dual threaded Xeon cores on one die, together with the L3 cache and ring interconnect. This is implemented in a 32nm cmos process with nine layers of metal. Addressing energy efficiency is the Godson-3B processor from the Chinese Academy of Sciences. This eight core design, implemented in 65nm cmos, has a peak double precision performance of 256GFlops and a maximum clock speed of 1.05GHz. It consumes 40W, delivering what the high performance digital committee say is 'an astonishing energy efficiency of 3.2GFlops/W'. Pushing the complexity boundary is Intel's 32nm Poulson processor.With 3.1bn transistors integrated on a die with an area of 544mm2, the device features eight processor cores and 54Mbyte of on chip cache, linked by an on chip ring like interconnect bus. High speed links allow for a peak interprocessor bandwidth of 128Gbyte/s and a memory bandwidth of up to 45Gbyte/s. However, the committee points to two other contenders for the highest level of integration. The 32nm Intel Sandy Bridge processor integrates four high performance x86 cores, an optimised gpu, a dual channel DDR3 memory controller and a 20lane PCIe interface. The 40nm AMD Zacate processor integrates two x86 Bobcat cores (each with a 512kbyte L2 cache), a dedicated Radeon HD5000 graphics and multimedia engine, a DDR3 memory controller, a client northbridge and a 4X PCIe link. Fine grained power gating, dynamic voltage/frequency scaling and enhanced display refresh are amongst the key enablers for low power operation. These and related topics will be discussed at length at ISSCC 2011, the foremost global forum for new developments in the integrated circuit industry. ISSCC will be held from 20 to 24 February 2011, at the San Francisco Marriott Marquis Hotel.