Jonathan Bakke, a global product manager within the company’s transistor and interconnect group, said: “Device performance is limited by interconnect wires; you have to get electrons from the battery to the transistor through all those interconnect layers. By the time you get to the contact, the wires are very small – less than half the width of copper wires – and very delicate. At the 10nm node, they may only be 10 to 15nm in width.”
Size is just one aspect; resistance is another. “Transistors are only as good as the electrons that get to them,” Bakke pointed out. Amongst the process steps currently in use is the deposition of a barrier layer to provide a base for tungsten fills, followed by a liner layer. “These are high resistance layers,” Bakke continued, “and any volume they take slows the transistor. But, while contacts are shrinking, the barrier layer can’t scale, so it is taking up more volume proportionately.”
Besides resistance, improper tungsten fills can create voids and seams, resulting in defects. “At the 20nm node,” Bakke said, “even defect levels of one part per billion can kill a device and bring a big yield loss.”
Applied Materials says Endura Volta, pictured, allows manufacturers to use one layer as a barrier and a liner, providing more room for tungsten fills. “It’s one less layer to deal with,” Bakke commented. “It also allows a 9nm fill, rather than the current 3nm. We’re focusing on this because plug resistance is becoming dominant at 10nm and we need to get it down.
Centura iSprint addresses the issue of voids. “It enables bottom up fill,” Bakke said, “and is the first bottom up CVD process in production.”
A chemical modification process prevents nucleation, meaning tungsten will not grow in treated areas. Because the treatment is graduated, with nothing at the bottom of the feature, tungsten will grow from the bottom up, filling the feature, rather than growing uniformly on the surface, as with current approaches.
