The MachXO3D FPGAs will augment the system control capabilities of the Lattice MachXO FPGA architecture with security features, including hardware Root-of-Trust (RoT), platform firmware resilience (PFR), and secure dual-boot support.
The MachXO3D and MachXO3LF devices target control, bridging, and I/O expansion applications that need to operate reliably in rugged environments, including advanced driver assistance systems (ADAS), infotainment, motor control, 5G communications infrastructure, industrial robots and automation systems, and defence systems.
MachXO3LF and MachXO3D FPGAs are supported by Lattice’s design software suite, Lattice Diamond, a GUI-based FPGA design and verification environment with design and implementation tools optimised for low-power Lattice FPGAs. The latest version of Lattice Diamond, version 3.11.3, is now available.
Key features of the new MachXO3LF and MachXO3D FPGA family include:
- Support for an extended operating range -40°C to +125°C (junction temperature)
- Robust control – provides instant-on control hub that reliably powers the platform up and power and simplifies deployment by:
- Single 3.3V or 1.2V supply operation
- Highest I/O-to-logic ratio
- Enables deterministic I/O operation by eliminating power-up glitches with default pull-down and maintaining signal integrity with program slew rate, drive strength, and hysteresis
The MachXO3D FPGAs’ security features include:
- On-chip flash memory – secures bitstream and user data against malicious attacks via OTP mode and password protection. MachXO3D has an immutable embedded security block to enable security compliant with NIST SP-800-193 Platform Firmware Resilience (PFR) guidelines for protecting, detecting, and recovering firmware from unauthorized access.
- On-chip flash enables single-chip, instant-on, and dual-boot images for fail-safe programming and in-field updates
- Flexible system with secure reprogramming - supports reliable in-system updates with:
Fail-safe reprogramming enabled by secure dual boot
- Configuration engine that prevents unauthorized access to configuration memory
- On-Chip flash that eliminates external memory and enables instant-on
- Mixed voltage support on I/O that eliminates GTL buffers and level shifters
- Per-pin programmability
