Developers will now be able to access and optimise performance across RISC-V-based multicore systems, including analysing the impact of shared resources and data coherency on worst-case execution time (WCET).
With mission-critical systems needing to be able to guarantee the reliability and deterministic execution of critical tasks, the tool suite now automatically analyses shared memory, cache resource access, coherency issues, and measures worst case execution time to guarantee deterministic execution time for RISC-V processors
With these tools, OEMs can now automate WCET analysis and make it part of a continuous development cycle. This WCET inclusion streamlines design, increases reliability and accelerates time-to-market and guarantees deterministic execution in software-intensive applications that require a high level of safety and security, including avionics, automotive, aerospace, defence, industrial, energy and medical.
“LDRA is committed to providing the tools manufacturers need to ensure safe, secure operation of mission-critical systems,” said Ian Hennell, Operations Director, LDRA. “We have been working with hardware manufacturers to reduce the complexity of analysing execution time for multicore architectures. Companies leveraging the RISC-V instruction set architecture have delivered innovative multicore mitigation capabilities, and LDRA provides the development tools to verify and guarantee that their performance meets the strict constraints required by today’s high performance real-time systems.”
Multicore processors accelerate performance by executing system code on different cores. In many multicore architectures such as traditional x86 and Cortex-A, cores share resources like cache and memory and to maintain data coherency, mediation between cores for shared resources is required. This means a core using a shared resource can unintentionally “lock out” other cores needing access to the same resource, resulting in an uncertain additional latency.
Mission-critical systems need to be able to guarantee the reliable and deterministic execution of critical tasks and so to ensure this, developers must accurately assess the worst-case execution time for a system.
New RISC-V-based processors introduce capabilities in hardware to help mitigate multicore shared access and data coherency issues. For example, Microchip RISC-V processors allow developers to allocate low latency memory to each core with zero shared cache contention.
The LDRA tool suite now supports multicore RISC-V architectures that address multicore contention in hardware. This support gives developers access to the full suite of LDRA tools, including static and structural coverage analysis, MISRA compliance and extensive reporting capabilities, all while taking full advantage of RISC-V-based multicore mitigation capabilities.
“Assessing shared resource access uncertainties can be complex, and many companies have had to rely on expensive consulting services to measure uncertainty in their systems to verify worst case execution time,” added Hennell. “Now developers can use the LDRA tool suite to automatically measure and analyse execution of RISC-V-based architectures to accurately and reliably guarantee execution time for mission-critical systems. In addition, automating analysis allows developers to quickly and inexpensively reassess systems after every code modification.”
