This collaboration is intended to enable mutual customers to streamline their RISC-V verification tasks using ImperasDV verification solutions and Synopsys’ VCS simulation and Verdi debug tools for improved efficiency to achieve critical time-to-market and quality objectives.
ImperasDV is the first commercially available verification IP for RISC-V processors including architectural validation test suites that RISC-V developers need to ensure hardware implementations are in line with the expectations of the software ecosystem supporting RISC-V.
It has native support for the open standard RISC‑V Verification Interface (RVVI) and uses a ‘lock-step-compare’ co-simulation methodology for comprehensive processor verification including asynchronous events and debug operations.
The RISC-V open standard ISA supports processors targeted at application solutions in new and creative ways. Design teams can utilise the new flexibility across all aspects of an SoC project with implementations targeted at internal control and management functions for power, security, communications and other tasks beyond the scope of a limited state machine.
RISC‑V is also seen as revolutionising the High-Performance Computing (HPC) design space with multicore arrays, vector accelerators, and complex pipelines featuring superscalar, out-of-order, multi-issue, and hardware multithreading, being among a a number of new design techniques.
The new design freedoms of RISC-V are resulting in a growing consensus across the SoC community that RISC-V verification requirements need to be integrated into SoC schedules and planning.
While processor verification may not be entirely new, RISC-V represents a massive shift in verification responsibility which in turn highlights the necessity for efficient verification to achieve key tape-out milestones and time-to-market targets. Any successful verification plan can be summarized as high-quality stimulus to achieve the coverage targets.
The combination of Synopsys VCS simulation and ImperasDV provides a seamless integration of testbench, processor RTL, and ImperasDV verification solutions in a combined SystemVerilog environment for ‘lock-step-compare’ co-simulation between the RTL design under test (DUT) and the Imperas RISC-V processor reference model. With this close integration, the debug at the point of discrepancy can be easily explored with a friction-free transition between the Verilog RTL and the Imperas RISC-V reference model using Synopsys Verdi and the Imperas eGui.
“RISC-V adoption is growing across key market segments as SoC teams explore the flexibility of an open standard ISA for optimised processors,” said Kiran Vittal, senior director of Partner Alliances Marketing for Synopsys EDA Group. “Our collaboration with Imperas, leveraging Synopsys’ leading simulation and debug solutions, enables our mutual customers to address verification complexities for RISC-V processor cores and quickly achieve coverage convergence.”
Simon Davidmann, CEO at Imperas Software added,“The Imperas reference models and simulation technology are structured for close integration within co-simulation and emulation environments. With this latest collaboration with Synopsys, our mutual customers can leverage all the advantages of the ImperasDV verification solutions with the advanced innovations in Synopsys VCS high performance simulation and Verdi debug platform for a complete SystemVerilog ‘lock-step-compare’ flow with efficient debug for RISC‑V verification.”
