Video, image processing, and FPGA design engineers can now speed up the exploration and simulation of behaviour and implementation trade-offs when processing 4k or 8k video and videos with resolutions of 240fps or higher.
Engineers designing FPGAs for real-time processing of high-resolution and HFR video in applications such as industrial inspection, medical imaging, and intelligence, surveillance, and reconnaissance (ISR) have to meet throughput, resource usage, and power consumption targets. The Vision HDL Toolbox offers blocks that can process 4 or 8 pixels in parallel, with the underlying hardware implementation automatically updated to support simulation and code generation with the specified parallelism.
This capability will help hardware engineers collaborate with image and video processing engineers to simulate vision processing hardware behaviour at a high level of abstraction. By adding HDL Coder to this design workflow, engineers can generate synthesizable, optimized target-independent VHDL or Verilog code directly from their verified high-level models.
“Implementing vision processing algorithms on FPGA, ASIC, and SoC devices requires clever trade-offs between throughput and resource usage, and 4k, 8k, and high-frame rate video multiplies this challenge,” said Jack Erickson, principal product marketing manager at MathWorks. “Exploring the solution space and simulating at a high level of abstraction helps engineers converge more rapidly on an architecture before committing to Register-Transfer Level (RTL). Vision HDL Toolbox and its native multi-pixel-per-clock processing automatically implement all the details so engineers can focus on developing hardware-ready algorithms that meet their requirements.”
Above: Vision HDL Toolbox helps to quickly explore processing 1, 4, or 8 pixels per clock. ©MathWorks
Vision HDL Toolbox provides pixel-streaming algorithms for the design and implementation of vision systems on FPGA, ASIC, and SoC devices. It provides a design framework that supports a diverse set of interface types, frame sizes, and frame rates. The video and image processing algorithms in the toolbox model hardware implementations that include latency, control signals, and line buffers.
The toolbox algorithms are designed to generate readable, synthesizable code in VHDL and Verilog (with HDL Coder). The generated HDL code is FPGA-proven for frame sizes up to 8k resolution and for HFR video.
