The solution looks to address applications such as data analytics, autonomous-driving and medical diagnostics that are currently driving extraordinary levels of demand for machine learning and hyperscale compute infrastructure.
Together with its XpressConnect retimers, Microchip claims to be the industry’s only supplier of both PCIe Gen 5 switches and PCIe Gen 5 retimer products, delivering a complete portfolio of PCIe Gen 5 infrastructure solutions with proven interoperability.
“Accelerators, graphic processing units (GPUs), central processing units (CPUs) and high-speed network adapters continue to drive the need for higher performance PCIe infrastructure. Microchip’s introduction of the PCIe 5.0 switch doubles the PCIe Gen 4 interconnect link rates to 32 GT/s to support the most demanding next-generation machine learning platforms,” said Andrew Dieckmann, associate vice president of marketing and applications engineering for Microchip’s data center solutions business unit.
The Switchtec PFX PCIe 5.0 switch family comprises high density, high reliability switches supporting 28 lanes to 100 lanes and up to 48 non-transparent bridges (NTBs). The Switchtec technology devices support high reliability capabilities, including hot-and surprise-plug as well as secure boot authentication.
With PCIe 5.0 data rates of 32 GT/s, signal integrity and complex system topologies are posing significant development and debug challenges, so to accelerate time-to-market, the Switchtec PFX PCIe 5.0 switch provides a comprehensive suite of debug and diagnostic features including sophisticated internal PCIe analyzers supporting Transaction Layer Packet (TLP) generation and analysis and on-chip non-obtrusive SerDes eye capture capabilities.
Rapid system bring-up and debug is further supported with ChipLink - an intuitive graphical user interface (GUI) based device configuration and topology viewer that provides full access to the PFX PCIe switch’s registers, counters, diagnostics and forensic capture capabilities.
Microchip has also announced the release of a full set of design-in collateral, reference designs, evaluation boards and tools to support customers building systems that take advantage of the high-bandwidth of PCIe 5.0.
