Director of SoC FPGA marketing Ted Marena said the core will be available on a royalty free basis, subject to a BSD license. “It’s an IP core with an Eclipse based soft console for Linux. We will also be launching a reference design. People are looking at RISC-V because it’s open. Collaboration is the norm amongst potential user and we expect there will be a lot of innovation.”
The RV32IM RISC-V core, developed in collaboration with SiFive, enables customers to design with an open instruction set architecture (ISA), enabling portability and a more secure processor architecture.
“We are very excited Microsemi is releasing a RISC-V intellectual property core for its FPGAs,” said Rick O’Connor, executive director of the RISC-V Foundation. “I applaud Microsemi’s leadership in introducing this comprehensive RISC-V platform and the foundation looks forward to working with the company to explore future advancements.”
Microsemi points to a number of benefits for using the RISC-V core: lower cost; security; safety; and innovation. “It’s lower cost because if you go to volume with a Cortex-M3 based design,” Morena claimed, “you will have to relicense it. And you can have multiple cores, so engineers could create a redundant design. For example, you could create a functionally equivalent, but independent RISC-V based core.” Security is said to be improved as the RISC-V RTL is open for inspection.
Suitable for use with all Microsemi FPGAs, the RISC-V core requires about 12,000 logic elements.
