The IP validation testchip and the HBM3 PHY were brought up within the first month to 6.4Gbps, and further tuning has resulted in successful operation of the HBM3 memory subsystem overclocked to 7.2Gbps.
To date, there are only a handful of IP vendors that have taped out and demonstrated HBM3 memory subsystems, as test shuttle and HBM3 DRAM die stack sample availability are both highly limited. OPENEDGES is now among the few companies to have demonstrated an HBM3 memory subsystem in silicon.
“Our confidence in the capabilities of our highly experienced engineering team allowed us to take on the extremely challenging HBM3 PHY IP and testchip development. We are very pleased to demonstrate the successful bring-up of our HBM3 testchip.”, said Farhad Haghighi Zadeh, TSS Principal Engineer and project lead for the HBM3 PHY and testchip.
The HBM3 PHY utilises state-of-the-art architecture to maximise timing and voltage margins over process, voltage and temperature variations, while minimising interruption to data traffic. The HBM3 PHY IP has the capability to support up to 16 independent and asynchronous channels, each with 2x32-bit DWORD pseudo-channels.
Additional features include fast frequency switching (multiple frequency set points), transient error handling (e.g. ECC, parity of data and command/address signals), as well as lane repair (Interconnect Redundancy Remapping), which detects, repairs, and remaps automatically in case of interconnect issues, making them transparent to the memory controller.
The development of an HBM3 memory subsystem is significantly different than that of other traditional DDR variants, as the memory controller/PHY SoC is in a 2.5D integration alongside the HBM3 die stack, the silicon interposer, and the package substrate.
There is a high degree of physical architecture coherency required such that the tens of thousands of SoC micro-bumps are assigned, connected, and verified correctly. As such, it requires sophisticated design of physical constructs to carefully handle intertwined dependencies across multiple layers of design hierarchy.
For example, the micro-bump array assignment would affect the PHY floorplan at the chip level, as much as it affects the RDL routings on the silicon interposer. On top of this, there is a persistent need for solid vertical delivery of power and grounds amongst a sea of signals; something that requires advanced planning - alongside the high-speed signal routings - as opposed to an afterthought.
The methodology used in the development of an HBM3 PHY testchip lend themselves very well to future chiplet designs. From the early physical planning on signal routings and power/ground deliveries, to co-planning of bumps and BGA balls along with the package substrate routings and planes, to the physical verification and cross-checks required; these are just some of the expertise and practical know-how required in the planning and development of an advanced memory subsystem chiplet.
“The successful validation of our HBM3 test chip is not just a milestone, but a testament to the value of our technology,” said Sean Lee, CEO of OPENEDGES Technology. “We continue to make significant progress in validating our IPs at the advanced nodes, taking further steps to empower our partners with superior performance and reliability”.
