Partners demonstrate ‘trail blazing’ DSP based on FD-SOI process

The device, produced by ST, allows body bias voltage scaling from 0 to 2V, decreases minimum circuit operating voltage and runs at 460MHz when using a 400mV supply. When the supply voltage is increased to 1.3V, the device is said to support a clock frequency of 2.6GHz. The demonstration circuit is said to achieve 'unprecedented levels of efficiency' in voltage and frequency. Both partners developed and optimised standard cells libraries over the 0.275 to 1.2V range: they are said to offer ideal implementation results by virtue of non overlapping power performance characteristics. On chip timing margin monitors adjust the clock frequency dynamically to within a few per cent of the maximum operating frequency, independent of supply voltage, body bias voltage, temperature and process technology. "This demonstration DSP shows that FD-SOI is blazing the trail for better portable and battery powered products, using more efficient semiconductor chips, all the way down to the 10nm node," said Philippe Magarshack, ST's executive vice president, design enablement services.