This new architecture can be seamlessly integrated in the digital design flow with industrial-grade qualification, overcoming integration drawbacks of existing ABB techniques.
Fully Depleted Silicon on Insulator (FD-SOI) is a technology that allows the biasing of the transistor’s body that acts as a back gate. Unlike conventional bulk technology, it enables a wide voltage range of the body bias which permits compensating for process, voltage, and temperature (PVT) variations by controlling the threshold voltage.
In switch operations, for example, when the switch is on, the body bias is changed to reduce the on-resistance by reducing threshold voltage and allowing more current to pass. That accelerates the circuit. In the off state, the body bias is changed to raise the off-resistance by increasing the threshold voltage, consequently reducing the leakage current. This shows that FD-SOI technology can be used either to accelerate the design or reduce the leakage power.
This new ABB technique, which was presented at ISSCC 2021, also allows the application design to maintain a targeted operating frequency over a wide range of operating conditions such as temperature, manufacturing variability and supply voltage.
The architecture enables reducing energy consumption of processors in 22nm FD-SOI technology by up to 30 percent and increasing the operating frequency up to 450 percent compared to a technique in which body biased technique is not used. It also improves the manufacturing yield.
“The ABB development is a breakthrough for FD-SOI technology because it shows the first-ever results depicting the enhancement in the circuit performance after using ABB, and it will help increase performances and yields in FD-SOI designs,” said Gaël Pillonnet, a CEA-Leti scientist and an author of the paper, “A 0.021 mm² PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FD-SOI Technology.”
The ABB is being commercialised by Dolphin Design, a specialist French company in modular and energy-efficient IPs, platforms and systems on chips (SoC). It is based on CEA-Leti’s proof of concept that was improved and industrialised by Dolphin Design.
According to the ISSCC paper, “the well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating VTH variability according to process corners and temperature. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm², with low-area and power overhead, e.g. 1.2% @ 2 mm² and 0.4% @ 10 mm², respectively.”
With this new architecture, the ABB area is relatively small compared to the application design, and in both area and power it allows the application design to maintain its targeted speed (frequency) with a relatively low overhead.
