The collaboration will allow CAES to provide next generation on-orbit reconfigurable processing systems for future satellite constellation.
The Certus-NX-RT and CertusPro-NX-RT FPGAs have been built on the Lattice Nexus platform delivering a combination of small form factor, system bandwidth and power efficiency – Lattice claims that it consumes up to four times less power in comparison with similar devices.
The 28nm devices feature temperature-resistant tin-lead (SnPb) terminations using a radiation-tolerant, fully-depleted silicon-on-insulator (FD-SOI) manufacturing process. CAES will qualify Lattice’s Certus-NX and CertusPro-NX FPGAs for radiation assurance and provide single-lot traceability and long-term supply.
The collaboration is intended to address the growing demand for reprogrammable, commercial off-the-shelf (COTS) programmable devices in satellite networks that require a high degree of redundancy and radiation tolerance.
“The space industry realizes that it can no longer rely solely on proprietary technology if it’s going to meet the growing affordability needs of satellites deployed in low- earth orbits,” said David Young, Chief Technology Officer, CAES. “Our collaboration with Lattice will promote the development of open, scalable, upgradable architectures that are compatible and affordable.”
“The collaboration with CAES will make it easier than ever for the space industry to achieve their design objectives with our low power, high system bandwidth, small form factor FPGAs that support satellite constellation networks,” said Esam Elashmawi, Chief Strategy and Marketing Officer, Lattice Semiconductor. “With our scalable Certus-NX and CertusPro-NX FPGA families and CAES’ deep industry expertise, we are accelerating the adoption of new architectures ideally suited for the evolving processing needs of today’s space applications.”
CAES experts will provide software programming and design support throughout the product development process. CAES will also offer pre-engineered IP building blocks and development tools including Lattice Radiant design software, which enable large, complex designs to be implemented efficiently and adds support for popular logic synthesis tools.
CAES is actively developing a port of its proven GRLIB development environment and a library of configurable, standardized soft IP design cores to further support customer needs as they integrate these FPGAs into their designs.
The production release of Radiant tools will be made available starting in the first quarter of 2022 with Certus-NX-RT FPGA samples planned for early second quarter of 2022 and Certus-Pro-NX-RT FPGA samples planned for the third quarter of 2022.
