Rambus is demonstrating the technology this week at its Developer Forum in Tokyo. It has fabbed a device on TSMC's 65nm process which Technical director Steven Woo says 'mimics what dram will look like in 2010'.
The system features a controller and two 'imitation' DRAMs. Woo says the system can sustain a bandwidth of 64Gbyte/s. “Driving data into the array and reading it back has to be done to prove the signalling will work." According to Woo, Rambus has been trying to figure out how to get Tbyte/s data rates in SoCs. “That means 16Gbit/s per DQ (data) link," he continued.
Woo said three key innovations underpin the initiative: a 32x data rate; the FlexLink command/ address (CA) link; and a fully differential memory architecture (FDMA). The 32x data rate is achieved by multiplying up a 500MHz clock to attain 16Gbit/s transfers. FlexLink replaces the legacy 12 wire controller to DRAM interface with a two wire point to point pair. Although it's possible to bus CA information to multiple drams, Rambus says many designers don't use this feature; rather, they run an identical set of wires to each memory.
“We decided it would be better to increase CA wire speed and reduce their number and we've matched bus speed to that of the data link," Woo claimed. FDMA has been implemented because single ended signalling was not robust enough, Woo noted. “The CA bus needs to be differential and this extends the work we've been doing. FDMA enhances signal integrity and this is key to the robustness of our approach."
