Reconfigurable logic technology to solve assp dilemma?

According to ceo Colin Dente, pictured, ART2 simplifies the design and implementation of reconfigurable chips by separating dataflow circuitry from control logic. "It works at higher level than an fpga," he noted, "and is more coarse grained. You build a reconfigurable data path by putting down processing elements such as add/subtract, multipliers and registers. You define which of these you need and interconnect them; that defines the hardware. There's a standard set of elements; it's the connectivity that can be changed." ART2 consists of a library of reconfigurable IP 'building blocks' claimed to be 'significantly larger' than similar offerings. This allows a greater degree of flexibility in how companies design reconfigurable functions, and enables a more efficient use of silicon area. "We have designed ART2 to be as simple to implement as possible", said Dente. "The potential of reconfigurable logic is vast, but it also has to be realistic for engineers to implement it easily. In the past, companies have gone for a 'fine grained' approach. We have built a comprehensive library of simple 'blocks' of reconfigurable IP that engineers can build around their central designs." The technology has been developed by people with background in telecoms and mobile devices, said Dente. "They understand the need for flexible signal processing, but also know that can't use an fpga in portable devices." Dente noted that Akya has looked at previous technologies labelled 'dynamically reconfigurable'. "Their mistake was to make general purpose devices; and people are still making them. Some companies can afford to design large, power hungry devices, but where they have tried to produce reconfigurable chips or IP, their problem is power and silicon area overhead." Akya's approach is to be generic. "Because all codecs are essentially Mpeg2 like or Mpeg4 like, you can define a set of resources that can decode any of those formats if they are connected in the right way." But he admits that silicon area will be bigger than that needed for a single codec. "But it won't be bigger than that needed for two." Operations are controlled by a sequencer on a clock by clock basis. "With an add/subtract unit," Dente noted, "you need to know what to do on each clock. That's handled by the sequencer. "You can have a situation where the data path changes on each clock cycle or you can set up a static data path," he offered. ART2 can be targeted at any process that accepts Verilog and which has single and dual port memories. "Because it's all done in Verilog, we can target any technology without needing to change the input code." One potential application for Akya's technology is providing flexibility for assp designers. "It could have application where a designer might want to build a number of devices, but can't afford to," he said. "We've talked with a big assp company which is having trouble making its products worthwhile at 65nm. By adding our technology, we give the ability to make variants without new silicon. It's a way of saving that business." Dente says Akya is working with a US company on a consumer oriented project and expects to see products being announced next year.