This marks a significant turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology.
According to the team, they also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
Samsung Foundry used the Tempus ECO Option within the Cadence Innovus Implementation System, which facilitated faster design convergence and closure, leading to a reduction in the project’s timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimising resource allocation and reducing machine and memory demands.
Finally, the Samsung team utilised Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.
“The successful tape-out of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics, Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”
According to Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence, “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”
