Ansys’ simulation solutions will be used to deliver a comprehensive EM-aware design flow with greater capacity, speed, and integration capabilities for Samsung’s advanced semiconductor technology, accelerating on-chip design cycle times to boost high-speed connectivity while helping to reduce design error and risk.
According to Samsung, its designers will leverage Ansys’ EM design tools, Ansys RaptorX, Ansys VeloceRF, and Ansys Exalto, to reduce time to market by two to three weeks on smaller designs and up to two months for complex designs.
With automation capabilities that optimise calculations and modelling, coupled with larger capacity, Ansys’ software will allow the Samsung team to design at faster speeds with higher fidelity.
“Electronic systems and process technologies are constantly evolving and therefore require leading-edge EM design capabilities,” said Sangyun Kim, corporate vice president of Foundry Design Technology Team at Samsung Electronics. “We believe that Ansys’ simulation solutions meet these challenges and will deliver the highest level of proficiency for our design needs, while reducing design time, cost, and risk.”
By integrating Ansys’ EM solutions, Samsung designers will be able to model complex on-chip scenarios, including dummy tiles, which comprise millions of metal pieces in a fraction of the time. In addition, Ansys’ near real-time modelling capabilities safeguard designs from EM interference, which helps significantly lower the risk of chip failure.
“EM is a primary challenge for chip designers as connectivity demands increase and technologies advance worldwide,” explained John Lee, vice president and general manager of the electronics, semiconductor, and optics business unit at Ansys. “At Ansys, we ensure that our simulation solutions not only meet these rising demands but remain ahead of them. We are confident that Ansys’ EM design portfolio is well-equipped to serve the Samsung team with the tools they need to optimise their on-chip designs.”
