The Cadence Tensilica cores supported in the first implementation phase are the Tensilica Xtensa LX7 CPU, a number of Tensilica HiFi DSPs (HiFi 4, HiFi 3z, HiFi 3, and HiFi 1), as well as the Tensilica Fusion F1 DSP.
The latest hardware versions of all commercial SEGGER J-Link models (J-Link BASE, J-Link PLUS, J-Link ULTRA+, and J-Link PRO) will now be able to support high-speed download and debugging of these cores via JTAG and SWD.
“The SEGGER J-Link is the most widely used line of debug probes in the market,” said Ivo Geilenbruegge, Managing Director of SEGGER, “and have provided solid value to embedded development for over 15 years offering an extensive feature set, a multitude of supported CPUs, and compatibility with popular development environments.”
“The drive to push intelligence further out to the edge means that more and more MCUs and SoCs contain our Tensilica CPU and DSP IP,” said George Wall, Group Director of Product Marketing for Tensilica Xtensa Processor IP at Cadence. “The new SEGGER implementation enables us to use the J-Link GDB Server as a native J-Link driver in our Tensilica Xplorer Integrated Development Environment (IDE), resulting in a significant performance increase. As a result, customers will be able to debug their firmware running on Tensilica cores more quickly.”
