The foundry's 12LP+ solution is optimised for artificial intelligence (AI) training and inference applications.
Built on a proven platform with a robust production ecosystem, the 12LP+ introduces new features including an updated standard cell library, an interposer for 2.5D packaging, and a low-power 0.5V Vmin SRAM bitcell that supports the low latency and power-efficient shuttling of data between the AI processors and memory. The result is a semiconductor solution that has been specifically engineered to meet the needs of the fast-growing AI market.
“Artificial intelligence is on a trajectory to become the most disruptive technology of our lifetime,” said Amir Faintuch, senior vice president and general manager of Computing and Wired Infrastructure at GF. “It is increasingly clear that the power efficiency of AI systems – in particular how many operations you can wrest from a watt of power – will be among the most critical factors a company considers when deciding to invest in data centres or edge AI applications. Our new 12LP+ solution tackles this challenge head-on. It has been engineered and optimised, obsessively so, with AI in mind.”
By partnering closely and learning from existing AI clients, GF has developed the 12LP+ to provide greater differentiation and increased value for designers in the AI space while minimising their development and production costs.
Driving the enhanced performance of 12LP+ are features including a 20-percent SoC-level logic performance boost over 12LP, and a 10-percent improvement in logic area scaling. These advancements are achieved in 12LP+ through its next-generation standard cell library with performance-driven area optimized components, single Fin cells, a new low-voltage SRAM bitcell, and improved analogue layout design rules.
12LP+ is also augmented by GF’s AI design reference package, as well as GF’s co-development, packaging, and post-fab turnkey services. Close collaboration between GF and its ecosystem partners has resulted in cost-effective development costs and a quicker time to market.
GF said that it will expand the IP validations for 12LP+ to include PCIe 3/4/5 and USB 2/3 to host processors, HBM2/2e, DDR/LPDDR4/4x and GDDR6 to external memory, and chip-to-chip interconnect for designers and clients pursuing chiplet architectures.
GFs’ 12LP+ solution has been qualified and is now ready for production at GF’s Fab 8 in Malta, New York. Several 12LP+ tape-outs are scheduled for the second half of 2020.
