According to Siemens, this is a comprehensive, automated signoff solution that provides quality assurance across all design intellectual property (IP) types, including standard cells, memories and IP blocks.
The solution provides complete quality assurance (QA) coverage across all IP design views and formats, as well as version-to-version IP qualification for more predictable full-chip IP integration cycles and faster time-to-market.
Integration of off–the-shelf design IP for next-generation semiconductor designs continues to expand due to both the quality-enhancing and time-saving advantages of IP reuse and modularization.
To achieve silicon success, however. all IP must be validated for correctness and consistency early in the design flow, as issues discovered late in the design cycle can result in costly tapeout revisions or silicon re-spins.
Design IP is articulated in multiple design views such as logical, physical, electrical, timing, and power analysis contexts. However, thoroughly validating IP across all these perspectives and formats can be particularly time-consuming, often leading to significant production schedule delays.
The Solido IP Validation Suite has been developed to reduce these delays by providing production and integration teams with automated, comprehensive and customisable IP validation capabilities.
The suite includes Siemens’ Solido Crosscheck software and Solido IPdelta software, both of which provide a comprehensive set of IP QA checks targeted for all types of design and foundational IP, incorporating in-view, cross-view, and version-to-version QA checks in a streamlined solution.
The Solido IP Validation Suite offers rapid, full-flow coverage QA for IP production and integration teams through advanced features like smart parsing for IP data re-use, additive IP QA for automatic change identification and merging of QA reports, and seamless integration with verification platforms like Siemens' Calibre platform.
“With the increasing importance of design IP in semiconductor design, efficient and correct IP validation becomes a critical step towards silicon success,” said Amit Gupta, vice president and general manager, Custom IC Verification, Siemens Digital Industries Software. "The Solido IP Validation Suite provides a scalable and repeatable solution to identify and prevent design-breaking issues, helping IP production teams achieve high-quality IP delivery at every iteration, and helping chip-level design teams achieve faster tape-out schedules with fully qualified, easier-to-integrate design IP.”
