For ASICs and chiplets using the latest and most advanced semiconductor packaging 2.5D & 3D technologies and substrates, Innovator3D IC provides a consolidated cockpit for constructing a digital twin - featuring a unified data model for design planning, prototyping and predictive analysis - of the complete semiconductor package assembly.
This cockpit drives implementation, multi-physics analysis, mechanical design, test, signoff, and release to manufacturing.
By unifying analysis tools, it enables rapid ‘what-if’ exploration, while identifying, avoiding and solving challenges prior to detailed design implementation. This shift-left approach can prevent costly and time-consuming downstream rework or suboptimal results.
“Siemens already had the most comprehensive portfolio of semiconductor packaging related technologies available as part of Siemens Xcelerator,” said AJ Incorvaia, senior vice president of Electronic Board Systems at Siemens Digital Industries Software. “By combining these with Innovator3D IC we enable customers to achieve the realisation of more-than-Moore.”
Innovator3D IC drives ASIC, chiplet and Interposer implementation using Siemens’ Aprisa software digital IC place and route technology, Xpedition Package Designer software, Calibre 3DThermal software, NX software for mechanical design, Tessent Test software, and Calibre 3DSTACK software for interchiplet DRC, LVS and tapeout signoff.
Innovator3D IC uses a hierarchical device planning approach to handle the massive complexity of advanced 2.5D/3D integrated designs with millions of pins. Designs are represented as geometrically partitioned regions with attributes controlling elaboration and implementation methods. This allows critical updates to be quickly implemented while matching analytic techniques to specific regions, avoiding excessively long execution times. Hierarchical interface route path planning further optimizes chiplet interfaces and pin assignments.
Although Innovator3D IC is integrated with the Siemens Xcelerator portfolio of industry software, its open architecture also supports integration with third-party point solutions.
A key tenant of Innovator3D IC is its support of industry standard formats, such as 3Dblox, LEF/DEF, Oasis and interface IP protocols (such as UCIe and BoW). Active participation in the Open Compute Projects Chiplet Design Exchange Working Group (OCP CDX) enables direct consumption of standardised chiplet models that will be provided by the emerging commercial chiplet ecosystem.
Innovator3D IC is also not limited to 2.5D and 3D integrations, as it is capable of planning and prototyping all leading and emerging semiconductor integration methodologies and platforms including interposers (organic, silicon or glass), ABF build-up, RDL based with chips first or last including support for Deca Technologies adaptive patterning process. It is also certified for Panel-Level-Packaging (PLP), embedded or raised silicon bridges as well as System-In-Package (SiP) and modules.
The Innovator3D IC solution is architected around the System Technology Co-Optimization (STCO) methodology process developed by IMEC and utilised throughout prototyping and planning, design, sign-off /manufacturing hand-off, concluding with a comprehensive verification and reliability assessment.
Siemens developed Innovator3D IC using the Next Generation Electronics Systems Design (NGESD) AI-infused User eXperience (UX) technology, which uses extensive multithreading and multicore capabilities to achieve optimal capacity and performance on 5+million pin designs.
Innovator3D IC is expected to be available later in 2024.
