Simulation system evaluates chip design faults with unprecedented accuracy
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MIT researchers have developed a software simulation system designed to evaluate multicore chip designs more accurately.
The research has been undertaken to address the increasing speed of chips, resulting in a need for more cores. MIT believes that if chips improve at the current rate – doubling in power roughly every 18 months – they will soon require hundreds or even thousands of cores.
An MIT group has developed a software simulator, dubbed Hornet, that models the performance of multicore chips more accurately that its predecessors.
The flow of data through a chip with hundreds of cores is extremely complex and previous software simulators have sacrificed some accuracy for the sake of efficiency. For more accurate simulations, researchers have typically used hardware models; programmable chips that can be reconfigured to mimic the behavior of multicore chips. The MIT researchers believe the Hornet complements these approaches, sitting in the 'sweet spot' between them.
The various tasks performed by a chip's components are synchronised by a master clock during each clock cycle and each component performs one task. According to MIT, Hornet is significantly slower than its predecessors, but it can provide a simulation of a chip with 1000 cores precise to the level of a single cycle.
Hornet is also designed to source extremely rare problems when evaluating a chip's performance. A recent presentation involved analysis of a promising multicore computing technique in which the chip passes computational tasks to the cores storing the pertinent data, rather than passing data to the cores performing the pertinent tasks. Hornet identified the risk of a problem called deadlock – in which some number of cores are waiting for resources such as communications channels or memory locations, in use by other cores - which other simulators had missed.
In addition to identifying the risk of deadlock, the researchers also proposed a way to avoid it – and demonstrated that their proposal worked with another Hornet simulation. That, says the MIT group, illustrates Hornet's advantage over hardware systems – the ease with which it can be reconfigured to test out alternative design proposals.
While the developers say that Hornet is slower than either hardware simulations or less accurate software simulations, it is suitable for locating abnormal behaviours.