MIT system makes hardware models of multicore chips more efficient, easier to design

Unlike competing methods, the process is said to guarantee that the simulator won't go into deadlock. It could also make it easier for designers to develop simulations and for outside observers to understand what those simulations are intended to do. To create the Arete system, the researchers took the approach of simulating a circuit's behavior in stages – using a partial circuit but spending eight clock cycles on a calculation that in a real chip would only take one. While this method has traditionally meant slowing down the whole simulation, the team developed a circuit design that allowed the ratio between real clock cycles and simulated cycles to fluctuate as needed. This was said to result in faster simulations and more economical use of the fpga's circuitry. According to graduate student Asif Khan, the system's success comes down to the fact that the team associated a little bit of memory with each input and output wire. Data coming in on a given wire was stored in memory until all the operations that required it had been performed; data going out on a particular wire was stored in memory until the data going out on the other wires had been computed. Once all the outputs had been determined, the input data was erased, signaling the completion of one simulated clock cycle. Depending on the complexity of the calculation the circuit was performing, the simulated clock cycle could correspond to one real clock cycle, or eight, or something in between. "The memory associated with the input and output wires and the logic to control it does take up some extra real estate on the fpga, but you only do it for select parts of the design, like complex logic, or these memories that you just cannot fit on chip on fpga's," said Khan. "And remember, through this overhead, you are able to save a lot of resource." Although other research groups have developed fpga multicore simulation systems that use space and time efficiently, Khan claims the Arete system is the only one that can guarantee their simulator won't deadlock. Another advantage, he says, is that it makes it easier for outside observers - and even chip designers - to understand what a simulation is intended to do. "With other researchers' simulators, it's often the case that the cycle level specification for the machine that they're modeling is in their heads," Khan explained. "What we're proposing is, instead of having this in your head, let's start with a specification. "Let's write it down formally but in a language that is at a very high level of abstraction, so it does not require you to write a lot of details. And once you have this specification that clearly tells you how the entire multicore model is going to behave every cycle, you can transform this automatically into an efficient mapping on the fpga." The researchers' high level language, which they've dubbed StructuralSpec, builds on the BlueSpec hardware design language developed in the late 1990s and early 2000s. The user gives a high level specification of a multicore model, and software spits out the code that implements that model on an fpga. Where a typical, hand coded hardware model might have about 30,000 lines of code, Khan says, a similar model implemented on StructuralSpec might have only 8,000 lines of code.