Recognising that processors and custom logic now work faster, the 100kHz bus frequency offered by SMBus 2.0 is complemented with two further speeds of 400kHz and 1MHz in version 3.0. This, in turn, has required the high power electrical drive levels to be adjusted and reorganised. The data hold time specification has also been changed to match the I2C specification; a move which is said to recognise that most devices on the market manage data hold time in accordance with I2C.
Version 3.0 also includes the removal of a specification for minimum immunity to noise on the clock and data lines as the SMIF Working Group found that no supplier of SMBus devices or system OEM using SMBus has tested against the parameter.
The changes to the SMBus specification will also support further improvements in the PMBus protocol standard and these will be incorporated in the PMBus 1.3.1 specification.
The SMBus is a two wire interface through which system component chips and devices can communicate. In addition to reducing pin counts and supporting a flexible and expandable environment, SMBus delivers a range of functionality, such as saving states from a suspended event and the reporting of errors.
