SRAM design consumes 50% less power than rival approaches
Early tests of SureCore's low power SRAM design are said to confirm the results simulations which suggested power savings in excess of 50% would be possible compared to other approaches.
Paul Wells, SureCore's CEO, said: "This is a tremendous achievement by our engineering team; right first time silicon at 28nm and performance measurements correlating exceptionally well with simulation. This demonstrates the immense capability of our technology and the expertise of our engineers to deliver next generation SRAM. Silicon verification of our design defines a major milestone in our relationships with partners and customers."
SureCore's energy efficient memory was designed through a combination of detailed circuit analysis, architectural improvements and the use of advanced statistical models.
The solution, which is technology independent and applicable to Bulk CMOS, FinFET and FD-SOI technologies, is likely to find interest from the mobile, networking and wearable technology markets.
