ST launches first embedded microprocessor to couple two ARM Cortex-A9 cores with a ddr3 memory interface

Manufactured in ST's 55nm high speed cmos (hcmos) process technology, the SPEAr1310 has been designed to deliver high computing power and customisability for multiple embedded applications. According to ST, the new microprocessor combines the low power and multiprocessing capabilities of the ARM Cortex-A9 processor core with Network-on-Chip (NoC) technology. ST reveals that the dual ARM Cortex-A9 processors support both fully symmetric and asymmetric operations, at speeds of 600MHz/core (industrial worst case conditions) for 3000DMIPS equivalent. NoC is a communications architecture that enables multiple different traffic profiles while maximising data throughput efficiently. "SPEAr1310 is the first device in the recently announced SPEAr1300 family and others will follow shortly," said Loris Valenti, general manager of ST's Computer Systems Division. "With its innovative architecture and powerful feature set, SPEAr1310 is at the leading edge of the embedded processor market and enables an unprecedented mix of cost competitiveness, performance and flexibility." The device is equipped with an integrated ddr2/ddr3 memory controller and connectivity peripherals. The microprocessor is targeted at high performance embedded control applications across market segments from communication and computer peripherals to industrial automation. Cache memory coherency with hardware accelerators and i/o blocks is designed to increase throughput, while the Accelerator Coherency Port (ACP), coupled with the device's NoC routing capabilities, aims to address the latest application requirements for hardware acceleration and i/o performance.