The expansion includes the launch of the S124 Group of Synergy Microcontrollers (MCUs) with ultra-low power operating characteristics and precise analogue signal acquisition/generation capabilities for sensor applications. In support of these MCUs is an updated version of the Synergy Software Package (SSP) and the e² studio Integrated Solution Development Environment tool. The SSP and e² studio tool are also said to incorporate enhancements that address the entire Synergy Platform adding capabilities for networking, industrial automation, power management and automated configuration to further save time for embedded system developers.
“This new S124 Synergy MCU Group is another example of platform growth that brings ARM Cortex-M0+ based MCUs to the lower end of the application spectrum while remaining completely scalable and compatible with the companion Cortex-M4 based Synergy MCU groups that we launched last year,” said Mark Rootz, marketing director of Renesas' Internet of Things BU. “Expansion of the SSP enables customers to migrate between all Synergy MCU groups as their needs change and still be able to re-use existing application code.”
Renesas says that the S124 MCUs consume 70.3µA per MHz of MCU clock speed for long battery life in low power and battery-powered portable applications. They are available in packages down to 4 x 4mm for space-constrained end-products. Typical applications include smart edge-node IoT sensors, home appliance control, and point-of-sale terminals.
Development support for the S124 MCUs and the DK-S124 development kit is provided in SSP version 1.1.0 and e² studio version 5.0. The SSP v1.1.0 is said to include enhancements for IPv6 networking and services for connected devices, BSD-compatible socket layer support, support for SSI audio and CAN communications, plus several additions to the Application Framework.
e² studio v5.0 is built upon the eclipse v4.5 and is said to include features to enhance automated guidance for starting Synergy Platform projects such as presenting all building blocks of a project in a graphical stack representation for simplification of workflow and providing visibility of overall memory usage.
