Synopsys, IMEC collaborate on 3d stacking
Synopsys and Belgian nanoelectronics research centre IMEC has have entered into a collaboration under which they will use Synopsys' TCAD finite element method tools for characterising and optimising the reliability and electrical performance of through silicon vias (TSVs). According to the companies, their collaboration will accelerate the development of 3d stacked ic technologies.
"We consider the availability of Synopsys' silicon proven finite element method tools to be an integral part of deploying 3d stacked ic technology," said Luc Van den hove, pictured, IMEC's president and ceo. "This collaboration will speed up the development of through silicon via technologies and will in turn facilitate the adoption of 3d stacked ics in the semiconductor industry."
While considered an emerging technology, 3d stacked ic complements conventional transistor scaling and allows multiple chips to be stacked and integrated into a single package. This technology reduces form factor and power consumption, and increases bandwidth of inter chip communication by minimising connections through the circuit board with high parasitic capacitance.
