Looking to address the problem, Synopsys has launched the DesignWare ARC SEM110 and SEM120D security processors, said by the company to protect systems against software, hardware and side channel attacks, as allowing designers to separate secure and non secure functions as part of a Trusted Execution Environment (TEE).
Angela Raucher, ARC EM product line manager, said: “Because a lot of companies designing IoT edge nodes are concerned about power, performance and area (PPA), they want to run cryptography in software, rather than hardware, so the device needs to be protected. However, security can’t be solved at the expense of PPA because developers want to provide long battery life.
“Threats can be seen at the network, chip and device levels and the key to the solution is to put in more layers of protection.”
The SEM processor cores are based on the 32bit ARCv2 instruction set architecture (ISA) and optimised for area and power efficiency. The SEM110 integrates a range of security technologies and can be implemented in an SoC as either a standalone secure core or as a single core performing secure and non-secure functions. The SEM120D adds DSP functionality, catering for applications such as sensor processing and voice identification in health care and IoT devices.
Key features of the devices include: resistance to side channel attacks; an enhanced memory protection unit, a tamper resistant pipeline with
instruction and data encryption, as well as address scrambling; and a watchdog timer to detect system failures, including tampering.
Raucher added: “The cores also include error correction functionality, which will detect fault injection techniques.”
