The functional safety certification spans from base microcontroller to high-performance DSP, each with a configuration option for FlexLock to provide increased random fault protection and developed following a robust safety process to protect against systematic faults. Tensilica Xtensa processors are suited for the automotive market and are tailored for AI, vision, radar, lidar, audio, vehicle-to-everything (V2X), and control applications.
“Cadence Tensilica FlexLock processors optimised for automotive applications are among the first in the industry to achieve full compliance with ASIL-D functional safety standards,” said Wolfgang Ruf, head of functional safety for semiconductors at SGS-TÜV Saar. “Certification to our comprehensive assessment in accordance with the ISO 26262:2018 standard for ASIL-D systematic and random fault avoidance is a testament to the high functional safety quality of Cadence’s IP.”
Key to ASIL-D compliance is the new FlexLock capability, which adds lockstep support to the flexible and extensible Xtensa processor architecture. Lockstep is a proven method for increasing safety in software execution by providing redundancy of the core logic at the hardware level. Not only does it provide the support needed to achieve ASIL-D certification, but FlexLock also gives design teams the ability to accommodate two cores running independently in ASIL-B solutions.
In addition, the FlexLock solution allows the option of running local memories and caches of two cores in lockstep, achieving greater levels of protection against memory faults.
“Higher levels of autonomy require more intelligent computing at the edge in automotive applications, which is driving the need for higher levels of functional safety,” said Larry Przywara, senior group director, Tensilica marketing at Cadence. “With the introduction of FlexLock capability, users of Tensilica controllers and DSPs can achieve the highest level of certification, ASIL-D, and the protection it brings against random hardware faults.”
As with other Xtensa processors, the ASIL-D certified cores can be customised using the Tensilica Instruction Extension (TIE) language, which allows the IP to be optimised for the specific application, combining the right level of performance with the highest levels of safety.
