Too late for a DATE with C!

Electronic system level (esl) tools may not have been adopted swiftly or extensively, but at DATE 2007 – held in Nice last month – most major oems were already committed to system level design. A keynote from Toshiba, plus presentations from NEC, ST Microelectronics and a host of others, confirmed they have embraced UML, behavioural synthesis, architectural exploration and hardware/software debug at the C model level. In most cases, the move has been driven by the need to start software development earlier than has been possible with conventional rtl design methods. The DATE exhibition highlighted the host of tools now available to support esl, and many are not from traditional eda vendors. Companies are finding their well proven graphical, algorithmic and modelling tools are eminently suitable for system level design. Some software centric embedded processor and configurable IP vendors too, such as MIPS and Tensilica, have quietly developed and successfully deployed esl tools. Meanwhile, the eda firms that have best kept pace with the silent shift to esl have repackaged their tools into ‘virtual platforms’.