Xilinx 'reinvents' fpga design environment to cope with increased system complexity
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Leading fpga developer Xilinx has undertaken a 'ground up' review of its design environment, creating the Vivado Design Suite – an IP and system centric design environment that will accelerate design productivity.
Tom Feist, senior director of marketing, said: "It's an exciting time for Xilinx. As our devices move to the centre of systems, we're faced with new challenges, including how to integrate complex systems and implement them. Vivado is all about improving designer productivity."
According to Feist, productivity is becoming an increasingly important parameter. "Device cost relates to complexity and productivity. With devices getting more complex, productivity needs to increase to keep the costs down."
Feist also claimed Vivado was an attempt to bring electronic system level design to the mainstream. It provides an integrated design environment with a new generation of system to chip level tools, built on a shared scalable data model and a common debug environment. Recognising increasing complexity, Xilinx has embraded industry standards, such as the AMBA4 AXI4 interconnect, IP-XACT IP packaging metadata, the Tool Command Language and Synopsys Design Constraints.
"We have tried to preview a lot of the technology," Feist noted. "For example, Vivado is built on top of the PlanAhead user interface and it also uses an existing data model, supporting partial reconfiguration."
Vivado has two main elements. It addresses integration thorugh IP and system centric integration with fast verification, while it accelerates implementation through hierarchical and deterministic closure automation.
A new place and route algorithm is also featured. Feist said: "Today's fpga tools have place and route based on simulated analysis algorithms. They put a design down, spread it out and then do local moves to improve timing. Vivado has a 3d timing engine based on what the big eda companies have done for multimillion gate asics."
Feist also noted that while Xilinx will not be scrapping its ISE design environment, 'more aggressive designs will see the benefit of Vivado'.
Vivado is currently available under an early access programme, but will be more widely available in the middle of the year, when version 2012.2 is launched. This will be followed by WebPACK and Zynq-7000 support.
