BiCS FLASH 3D memory stacks flash memory cells vertically on a silicon substrate to realise density improvements over planar NAND flash memory, where cells are formed on the silicon substrate.
Devices fabricated with TSV technology have vertical electrodes and vias that pass through silicon dies to provide connections, an architecture that is said to realise high speed data input and output while reducing power consumption.
According to the company, combining a 48-layer 3D flash process and TSV technology enables an increase in product programming bandwidth while achieving low power consumption.
The power efficiency of a single package is said to be twice that of the same generation BiCS FLASH memory fabricated with wire-bonding technology. TSV BiCS FLASH is also said to enable a 1TByte device with a 16-die stacked architecture in a single package.
BiCS FLASH 3D memory is suitable for storage applications requiring low latency, high bandwidth and high I/O/s/W, including high end enterprise SSDs.
Shipments of prototypes for development purposes started in June, and product samples are scheduled for release in the second half of 2017.
