Toshiba develops silicon nanowire transistor for 16nm generation

The company has achieved a 1mA/µm on current - said to be the world's highest level for a nanowire transistor - by reducing parasitic resistance and improving the on current level by 75%. This is a major step towards practical application of nanowire transistors. Transistors with a 3d structure – including silicon nanowire transistors - are being investigated as candidates for future generations of devices, to help secure circuit reliability for smaller scale current planar transistors. A silicon nanowire transistor can suppress off-leakage and achieve further short-channel operation, because its thin wire-shaped silicon channel (nanowire channel) is effectively controlled by the surrounding gate. However, parasitic resistance in the nanowire-shaped source/drain, especially in the region under the gate sidewall, degrades the on-current. Toshiba says it has addressed this problem by optimising gate fabrication and reducing the thickness of the gate sidewall, from 30nm to 10nm. According to Toshiba, low parasitic resistance was established by epitaxial silicon growth on the source/drain with a thin gate sidewall, which lead to a 40% increase in on-current. The company says it achieved a further 25% increase in current performance by changing the direction of the silicon nanowire channel from the to plane direction. With the new technologies, Toshiba claims to have achieved an on-current level of 1mA/µm, when the off-current is 100nA/µm, a 75% increase in the on-current at the same off-current condition.