TSMC releases ‘unified and interoperable’ eda files

Responding, TSMC has released a number of 'unified and interoperable' eda files for its 65, 40 and 28nm process nodes. The design technology file suite includes interoperable process design kit (iPDK), interoperable design rule check (iDRC), layout versus schematic (iLVS) and interoperable interconnect extraction (iRCX). The technologies have been developed and validated in association with TSMC's eda partners as part of the Interoperability Project, itself a part of the company's Open Innovation Platform. "TSMC collaborates with multiple eda vendors to create and validate interoperable formats that accelerate data delivery and ensure the integrity and accuracy of advanced process technology data," said ST Juang, TSMC's senior director of design infrastructure marketing. "The unified eda data format provides designers with the ability to select qualified eda tools that match their design needs, improve compliance with TSMC processes and ensure design accuracy for first-time silicon success." TSMC collaborates with major EDA ecosystem partners who are part of the OIP Interoperability Project to define and develop a unified architecture and interoperable formats based on TSMC process requirements. The company's EDA partners support the new format in their tools and qualify tool accuracy against actual silicon measurements. This qualification process eliminates data inconsistency, reduces tool evaluation time and improves design accuracy. The 40nm iDRC/iLVS files were developed with Mentor and Synopsys, with QA and validation by Magma and Cadence. The 65nm iPDK was developed with Synopsys and Ciranova, with QA and validation by Magma and Springsoft.