The move is intended to accelerate the integration of heterogeneous dies to enable the next level of system scalability and functionality.
Synopsys provides a range of EDA and IP solutions for multi-die systems on TSMC's advanced 7nm, 5nm and 3nm process technologies with support for TSMC’s 3DFabric technologies and 3Dblox standard.
The integration of Synopsys’ solutions and Ansys multi-physics analysis technology on TSMC processes will help designers to tackle the challenges around multi-die systems, from early exploration to architecture design with signoff power, signal and thermal integrity analysis.
"Multi-die systems provide a way forward to achieve reduced power and area and higher performance, opening the door to a new era of innovation at the system-level," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "Our long-standing collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys and Ansys gives mutual customers a faster path to multi-die system success through a full spectrum of best-in-class EDA and IP solutions optimised for our most advanced technologies."
"The inflection point of silicon designs moving towards multi-die systems poses new challenges in power, thermal integrity and reliability signoff," explained John Lee, VP and general manager at Ansys. "These complex challenges require an integrated approach and a strong ecosystem to provide comprehensive solutions. Through our collaboration with Synopsys and TSMC, designers can leverage the full strength of our leading multi-die solutions and decades of expertise to accelerate silicon success."
"The transition to multi-die systems triggers profound changes, requiring a holistic approach that addresses die-to-die connectivity, multi-physics effects and die/package co-design," added Sanjay Bali, VP of Strategy and Product Management at Synopsys "Our collaboration with TSMC and Ansys delivers the industry's most comprehensive, scalable and trusted solutions to accelerate heterogeneous integration with reduced risk."
The Synopsys Multi-Die System Solution enables early architecture exploration, rapid software development and system validation, efficient die and package co-design, robust and secure die-to-die connectivity and enhanced manufacturing and reliability.
Key highlights of the collaboration include:
Synopsys 3DIC Compiler, a unified multi-die co-design and analysis platform that integrates with TSMC 3Dblox standard and TSMC 3DFabric technologies for 3D system integration, advanced packaging and a complete exploration-to-signoff implementation.
Synopsys signoff solutions, certified for the TSMC technologies and integrated with Ansys RedHawk-SC Electrothermal multi-physics technology, to address the power and thermal signoff critical for multi-die systems.
The successful tape-out of the Synopsys Universal Chiplet Interconnect Express (UCIe) PHY IP on the TSMC N3E process. UCIe is poised to become the de facto standard for low latency and secure die-to-die connectivity.
