TSMC says 32nm process supports analogue and digital
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TSMC says it has developed the first 32nm process that supports both analogue and digital functionality. The announcement, made at the International Electron Devices meeting, also revealed it had proven the full functionality of the 2Mbit sram test chip with the smallest 32nm bit cell.
"TSMC continues to lead the industry by pushing the boundaries of advanced technology," said Dr Jack Sun, vice president of R&D. "The achievement made at 32nm technology node is yet another testimony to our long-term investment and commitment in advanced technology development to help our customers in bringing their leading edge products first to market."
TSMC claims this is the first 32nm low power technology which does not require high k gate dielectric and metal gates to achieve its performance characteristics. It adds that a 0.15µm² high density sram cell has been created with double patterning 193nm immersion lithography.
The process is optimised for low power, high density and manufacturing margins with optimal process complexity and cost management. Low power technology integrated with high density sram, low standby transistors, analogue and rf functions. With and copper and low k interconnects, the process is said to be suitable for SoCs for mobile applications.
