TSMC to unveil 22nm process
TSMC will unveil a complete high performance 22/20nm cmos logic technology at the International Electron Devices Meeting, which takes place in San Francisco from 6 to 8 December.
The technology features FinFET transistor architectures, aggressive 193nm immersion lithography, SiGe stressors, metal gates and high K dielectrics.
According to prereleased information, the FinFETs have been built with dual epitaxy and multiple stressors. This has said to result in 'outstanding performance' in both n- and p-channel versions.
TSMC researchers have already used the process to build a dense 0.1µm2 sram cell.
