Updated place and route package set to bring x10 performance boost to chip design

Saleem Haider, pictured, senior marketing director for physical design and DFM, said: "It's exciting times for Synopsys and the introduction is turning out to be a big hit with early customers." One of the early customers referred to by Haider is Imagination Technologies. Mark Dunn, executive vice president of SoC Engineering for IMGworks, said: "Imagination has long been an early adopter of advanced design planning technology that delivers tangible results. Thanks to some unique design planning capabilities offered by IC Compiler II, we observed a boost to the throughput of our design exploration flow by at least x10. As a result, we realised a high quality floorplan for one of our latest PowerVR Rogue GPU cores in a fraction of the time we'd normally assign for this task." IC Compiler II has been built on a new multithreaded infrastructure, capable of handling designs with more than 500 million instances. It has a new global analytical optimisation engine, a new clock generator and innovative algorithmic capabilities in post route optimisation. However, some features from IC Compiler have been retained, including the conjugate gradient placer and the ZRoute router Haider noted: "We're staying pragmatic and using best pieces we have in place, so IC Compiler II includes the placement engine and Zroute. This keeps interface with foundries and silicon technology unchanged." The redesign, which has been in progress for about five years, was driven by the need to provide an increase in design throughput. "Even an x3 increase in speed will be significant," he claimed, "because design turn round can take many days. "We adopted an approach for the upgrade in which everything was on the table. The result could be 'game changing'," he contended. "The immediate application is to speed throughput – one day, instead of five or six, for a 2million cell design." The development process also benefitted from Synopsys' recent acquisition of Magma. "This not only brought some technology, it also brought some people," said Haider. Meanwhile, IC Compiler will continue to be maintained on a nine monthly upgrade cycle. "IC Compiler II will be more applicable to designs with more than a few hundred thousand cells," Haider noted. "While it will speed smaller designs, companies may not wish to invest in saving a couple of hours. But IC Compiler II will be suitable at the low end if customers want to do a lot of design exploration."