The ability to create more complex devices at the leading edge brings with it the challenge of realising those designs. Designers need to balance such parameters as timing, area, power, signal integrity and routability in order to meet the overall design requirements for the project.
In general, this phase is known as place and route, or P&R. Synopsys has been developing IC Compiler for some time to meet this need. IC Compiler is a physical implementation tool that includes flat and hierarchical design planning, placement and optimisation, clock tree synthesis and routing in order to help designers to implement complex designs on schedule.
The problem with larger designs, however, is meeting that schedule. As chips get larger, the computation time required has grown out of proportion, to the point where it can take many days to run a design. Looking to speed the process, Synopsys has launched IC Compiler II, described by the company as 'a complete netlist to GDSII P&R system that enables 10X faster throughput for designs across all process nodes'.
Saleem Haider, Synopsys' senior director of marketing for physical design and design for manufacture, said: "It's turning out to be a big hit with our early adopters. A tenfold increase in speed is exciting them."
Haider claimed IC Compiler has grown to be the most popular package of its type, with two out of three designers using it. "It's been that way for a number of years," he added. "It's popular for use with high performance designs and at emerging nodes."
But, despite being updated every nine months, IC Compiler was running out of steam when it came to larger designs and those at the leading edge. "We've developed IC Compiler II to provide a big jump in design throughput in terms of turn round time," he added. "A doubling or tripling of speed will be significant because turn round can be many days."
IC Compiler II has been in development for about five years. "We asked what more could we do?" Haider explained. "Could we enable an order of magnitude improvement in productivity?" The team adopted a two part strategy: not only to keep IC Compiler at the forefront; but also to embark on a speculative initiative in which 'everything was on the table'. "The latter is what's resulted in IC Compiler II," he said, "which brings faster performance with the same or better quality results. This can be 'game changing'; turning a design in one day, rather than five or six, is compelling."
Haider said the first issue to be addressed was to rebuild the package's infrastructure. "That's the foundation on which the system would be built; it determines the data exchange rate between the various parts of the system. These key components allowed us to rethink critical parts of the flow." Haider noted that elements such as the hierarchy, timers and optimisation were new, as was the approach to clocking. "All of these are key engines," he pointed out.
However, there was also the need for reuse. "We wanted to stay pragmatic," he claimed, "by using the best pieces we had in place, which included the placement engine and Zroute routing tool. This kept the interface with foundries and with silicon technology unchanged."
IC Compiler II has a new multithreaded infrastructure, capable of handling designs with more than 500million instances. It supports industry standard input and output formats, as well as familiar interfaces and process technology files, while introducing what Synopsys calls innovative design storage capability. The improved performance allows designers to evaluate more floorplanning alternatives, while the new elements, including the clock generator enhance the quality of results (QoR) for area, timing and power.
Haider said coarse placement of designs was twice as fast in IC Compiler II, 'even though it's existing technology'. "The data structure is better," he contended. Also included is a new design planning structure. "Part of the redesign was to be able to build high capacity designs and IC Compiler II can handle designs with up to 2billion gates."
The key to the improved performance, in Haider's opinion, is abstraction. "Being able to abstract to different levels in the hierarchy means you can apply and plan without needing all the details; it brings a significant increase in speed." In fact, Haider pointed to an x10 boost in design planning throughput, but added this performance required five times less memory than IC Compiler.
The overall performance is enhanced by taking a global perspective. "The basic approach was to look more globally at the design." The current approach looks at the logic more locally, then works towards a global target.
What Synopsys refers to as global optimisation is also a contributor to better performance, achieved through an approach called analytical physical synthesis, or APS. "This is a big step forward," Haider claimed. "Global optimisation allows you to look at more of the design at the same time. Because you don't need to retime the design again and again, it's also more oriented towards multithreading."
In a similar approach, IC Compiler II features a completely new clock tree construction. "It looks at the design more globally," Haider said, "and its network solver comes up with optimum values for latency and skew."
IC Compiler II is likely to be used in a number of ways. For those companies designing large chips, the package can be used to speed turn time. "If you have a 2million cell partition," Haider observed, "you could do this in the same day, rather than taking five. Also, instead of turning a small partition in one day, companies might want run larger design partitions."
The development of IC Compiler II has benefitted from acquisitions, particularly that of Magma. "But it's fundamentally new research," Haider concluded.
