The first full silicon solution from VSORA, Tyr uses the company's AD1028 architecture which is capable of delivering between 258-trillion and 1,032-trillion operations per second and consuming as little as 10W. Tyr is said to be able to allow users to implement autonomous driving functions that were previously not commercially viable.
The Tyr family comprises of three different chips called Tyr1, Tyr2 and Tyr3, and offers a fully programmable architecture that tightly couples digital signal processing (DSP) cores with machine learning (ML) accelerators necessary to design L3 through L5 autonomous driving vehicles. The Tyr companion chip is algorithm and host processor agnostic and can be integrated into new or existing environments without the need to redesign the entire system.
“We are proud to be the first to offer the ability to rapidly move to full autonomy utilizing what designers have already invested in,” said Khaled Maalej, CEO and founder of VSORA. “The Tyr family is the first in a series of companion chips from VSORA to provide global vehicle manufacturers early commercial availability of L3 to L5 functionality.”
The modular architecture of the Tyr family has been designed to meet the challenges associated with autonomous driving. With a computational power of 1,032 TeraFLOPS, the Tyr3 processes an eight-million cell particle filter using 16-million particles in less than 5 milliseconds (msec). For example, a full-high-definition (FHD) image with Yolo-v3 takes less than 1.6 msec leading to a throughput of 625 images per second.
Using VSORA’s proprietary low-power architecture the Tyr chips are able to achieve more than 80% usage efficiency approximating the theoretical maximum processing power, eliminating the need for expensive multi-chip or hardware accelerator solutions or special cooling solutions.
