This is the first full qualification of Weebit ReRAM technology, a key step required by every semiconductor product on each new target process.
The qualification, using Weebit’s demo chips incorporating its ReRAM module, was performed based on JEDEC industry standards for non-volatile memories (NVMs) and confirmed the suitability of Weebit’s embedded technology for volume production.
The JEDEC standards impose testing of silicon dies blindly selected from three independent wafer lots, as well as collecting a significant data set for detailed analysis. Obtaining in-depth statistics with a standards-based approach is key to showing the maturity of Weebit’s ReRAM.
All the dies successfully passed the entire set of qualification tests, demonstrating the quality, repeatability and reliability of Weebit’s ReRAM, and confirming its suitability for volume production as embedded IP.
The results of the qualification show high endurance, long data retention before and after endurance testing, as well as industrial-grade high-temperature stability:
- High endurance: 10K cycles (flash equivalent) endurance
- 10 years’ data retention before and after endurance testing
- Industrial-grade high-temperature stability – up to 85°C
- 3x SMT cycles (by itself a powerful retention test)
Weebit is now working to extend the qualification to even higher temperatures and endurance levels.
Commenting Coby Hanoch, CEO of Weebit Nano, said, “Successfully completing full qualification of our technology is a major milestone. Leti’s state-of-the-art fab makes these qualification results significant and relevant for other foundries and potential customers and could be used by customers as a baseline for their qualification process.”
The Weebit ReRAM demo chip comprises a full sub-system for embedded applications, including the Weebit ReRAM module, a RISC-V microcontroller (MCU), system interfaces, memories and peripherals.
The ReRAM module includes a 128Kb ReRAM array, control logic, decoders, IOs (Input/Output communication elements) and error correcting code (ECC) and is designed with patent-pending analogue and digital smart circuitry running smart algorithms that significantly enhance the memory array’s technical parameters.
