An ACAP is a highly integrated multi-core heterogeneous compute platform that can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads and can be done dynamically during operation.
The ACAP is intended to accelerate a broad set of applications in the emerging era of big data and artificial intelligence, such as: video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration. According to the company both software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications.
The first ACAP product family, codenamed “Everest” will be developed in TSMC 7nm process technology and will tape out later this year.
“This is a major technology disruption for the industry and our most significant engineering accomplishment since the invention of the FPGA,” said Victor Peng, president and CEO of Xilinx. “This revolutionary new architecture is part of a broader strategy that moves the company beyond FPGAs and supporting only hardware developers. The adoption of ACAP products in the data centre, as well as in our broad markets, will accelerate the pervasive use of adaptive computing, making the intelligent, connected, and adaptable world a reality sooner.”
At its core the ACAP has a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). It also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant.
Software developers will be able to target ACAP based systems using tools like C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools.
ACAP has been under development for four years at an accumulated R&D investment of over $1billion.Software tools have been delivered to key customers and Everest, which is expected to achieve 20x performance improvement compared to today's latest 16nm Virtex VU9P FPGA will tape out in 2018 with customer shipments in 2019.
