Versal ACAP, developed by Xilinx/AMD, is an adaptable platform comprising an AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and hardened domain-specific IPs such as PCIe Gen5 with DMA and CCIX, HBM, 600G Interlaken and 600G Ethernet.
The Versal ACAP enables heterogeneous computing of complex algorithms and accelerates workloads, such as artificial intelligence, embedded computing, and high-performance computing.
Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis hardware emulation flow for testing the interactions between AIE, PS, and PL. The entire hardware emulation setup and system integration is done within the Vitis environment. Vitis runs the AIE simulator for the graph application, the Riviera-PRO simulator for the PL kernels, and QEMU (open-source system emulator) for the PS host application. SystemC models are also available for the AIE and NoC, and they can be simulated in Riviera-PRO too.
System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density. The full system design can be tested with full debug visibility much earlier in the project cycle without any physical hardware, making it easier to run more test scenarios, test corner cases, and debug complex problems.
Users will be able to take advantage of Riviera-PRO’s high-performance mixed-HDL simulation engine, advanced debugging environment using waveform viewer, advanced dataflow, RTL hierarchy, objects viewer, and verification coverage features such as code coverage and functional coverage.
Riviera-PRO’s comprehensive support for SystemVerilog and UVM is beneficial to users who need to develop reusable and complex testbench environments.
“The Versal ACAP architecture is revolutionary in the FPGA domain, and a game-changer for heterogeneous computing”, said Louie De Luna, Aldec’s Director of Marketing. “With Versal, users can customise their own domain-specific architectures for optimised computations of their specific workloads. We are now stepping into the computing era where the differentiation is done in hardware instead of software.”
The majority of FPGA projects are notorious for having at least one non-trivial bug escaping into production, and simulation-based verification is a key aspect in minimising bug escapes.
System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.
Several Versal ACAP tutorial designs and steps on how to use Riviera-PRO as the RTL simulator for the Vitis hardware emulation flow can be found on Aldec’s Github.
