The compiler is said to allow designers to trade off the number of words, word length and multiplex factor. Supporting single and dual port SRAM IP, the compiler allows designers to select capacities up to 1Mbit, word lengths of up to 288bit and support for mux factors of 4, 8 and 16. It also generates datasheets, simulation, layout and timing/power models automatically.
“The availability of this compiler marks a key milestone for sureCore and demonstrates the power saving technologies we developed are now available to the SoC design community,” said sureCore’s chairman Guillaume d’Eyssautier.
The single port SRAM IP, which works from a supply between 0.6 and 1.2V, is said to have a dynamic power consumption that is more than 50% less than other offerings, while static power is said to be up to 35% lower.
The company plans to introduce a 40nm ultra low power compiler in March 2016 and says a 40nm CMOS ultra low power SRAM will arrive later next year. A 28nm CMOS solution is also being developed.
“There is still considerable innovation happening at relatively mature production nodes,” claimed sureCore’s CEO Paul Wells. “Mature nodes, such as 40nm are 28nm. are taking on an extended life [and] their cost performance is ideal for the IoT’s technical and business challenges.”
In May 2013, sureCore won a £250,000 SMART award from InnovateUK to help develop its low power SRAM technology and produced a demonstrator chip in October of that year using STMicroelectronics’ 28nm FD-SOI process.
