Outlook 2013: Accelerating innovation and time to market

What's interesting is that the pace of these innovations is not slowing; they are actually accelerating. Why would that be? It turns out that, despite the fact that Moore's Law advances at such a consistent rate – it is a law, after all – the products and markets that it enables evolve in waves. For the last 30 years, we have been riding a huge wave defined by the pc as the dominant computing platform and planar cmos as the dominant semiconductor technology. Innovation consisted of incrementing those platforms – pcs got better and better, with better graphics, faster processors and more memory, while cmos got faster and cheaper by narrowing the channel. During the pc/cmos era, it was pretty easy to see and plan for the future. Now we are entering a new phase. We are solidly in the post pc era, with billions being spent by companies to define and lead the next generation of computing. The planar cmos era is also ending, with all major semiconductor manufacturers spending billions to develop FinFETs and announcing FinFET capability in the near future. This change puts great stress on EDA's customers. If they out innovate their competitors and catch the public's attention, they could lead in this next era. If they do not, they could cease to exist. Synopsys sees this in its research, which shows the number one concern amongst its customers is meeting time to market schedules. They must accelerate their innovation to prosper – and they expect the same from their EDA, IP and services partners. Companies like Synopsys have responded with a burst of new tools and methodologies. It is not an exaggeration to say that companies trying to design leading edge chips today in the same way they did just three years ago are going to fail. Every part of the design flow is changed. Innovation in implementation Implementation – the process of designing the chip itself – is driven by three major challenges. * Gigascale Design. Today's designs are huge, with billions of transistors, yet engineers are required to design these chips to shorter schedules. To meet these schedules, digital designers must adopt new tools and methodologies such as: early exploration, where the engineer can quickly optimise the architecture and floorplan; look ahead optimisation, which ensures that decisions early in the flow correctly reflect what happens in later stages; automated constraint management, to ensure the instructions to tools are consistent and correct; and hyperscale technology that can handle hundreds of millions of instances of signoff. And that's just a few. The design of analogue blocks is also a huge challenge at lower geometries, where design margins are much tighter. The solution here includes: streamlined analogue mixed signal (AMS) verification; analogue and digital co design methodology; transistor level reliability analysis; and highly accurate transistor level modelling to provide high confidence in transistor level simulation results. Unlike its digital counterpart, the analogue design tool space has been closed and non interoperable. This lack of competition has slowed innovation to a crawl. The most important development in analogue design is the creation of interoperable libraries and tools which will spur competition and innovation. The leading effort here is the IPL alliance, which includes major foundries and EDA companies. * Gigahertz. Consumers want ever faster chips, so the race for higher frequency designs is on – again. Designers who leverage unique physical guidance technology integrated across tools, unique optimisations and specialised methodologies can achieve the high gigahertz frequencies they want. * Giga-complex geometries. Substantial changes have taken place with each move to a smaller geometry. To keep up with Moore's Law, new manufacturing and lithography techniques are needed to make today's chips. These techniques include double patterning, which affects every step of the design flow; 3D-IC; and FinFET. Adopting platforms that support these technologies can help designers keep up with the move to 20nm and smaller geometries. Innovation in verification The verification challenge is an exponential one in terms of time and cost. In an attempt to keep up with verification requirements, compute farms have doubled in size over recent years, verification teams have grown to twice the size of their design counterparts and the debug process now accounts for 35% of the verification effort. The typical verification profile of a state of the art design presents some staggering metrics – such as tens of millions of lines of RTL and testbench code, hundreds of thousands of assertions and terabytes of coverage data to analyse. To accommodate the dramatic shift in the design landscape, designers need innovations that focus on key productivity bottlenecks and which deliver significant improvements in performance and capacity. For example, superior, more intuitive debug that enables engineers to quickly analyse vast amounts of data and find design bugs; comprehensive, proven verification IP that is fast, efficient and timely; and innovative low power verification solutions. Innovation in designing with IP The use of preverified semiconductor IP in SoCs can help address the challenges associated with the exponential increase in content and data. Today's average chip contains outsourced IP worth a few million dollars; that's a bargain, compared to the cost of creating a chip from scratch. Strong points for EDA include interface IP, embedded memory IP and high quality analogue IP. To accelerate design innovation in IP, Synopsys is looking to offer subsystems that integrate multiple IP blocks with software in preverified solutions. An audio subsystem, for example, consists of hardware that is configurable and tailored to application requirements; complete audio system software that can plug seamlessly into an application host; a virtual prototype, to enable early and easy software development; an FPGA reference design that serves as a complete implementation platform; and IP integration services. By offering designers a configurable, SoC ready solution, a subsystem reduces the SoC design and integration effort significantly, lowers design risk and accelerates time to market. Innovation in prototyping Today's killer electronic system level (ESL) app is a prototype – a fast system model executing unmodified production code and providing higher debugging/analysis efficiency. With so much more software on a chip, the semiconductor industry must consider new approaches to tighten the hardware/software relationship. Typically, software is developed weeks or months after the chip is finished and a company can't get revenue from the chip until the customer's software is complete. The way to address this problem is to use a virtual prototype or FPGA based prototype that can enable software development before the physical chip is complete. By doing so, a chipmaker can get a chip to market six to 12 months earlier than was previously possible. Accelerating innovation Innovation doesn't happen in a vacuum: it takes massive investments in R&D, hiring the best engineers and working closely with customers. It also requires collaboration with stakeholders throughout the semiconductor design ecosystem in as open a fashion as possible so the benefits of innovation can extend across the industry. Whether our customers are designing mobile phones, automobiles, engine controllers or medical devices, accelerating innovation is an imperative to successfully meeting time to market goals. Synopsys Synopsys provides products and services that accelerate innovation in the global electronics market. A recognised leader in electronic design automation and semiconductor intellectual property, Synopsys employs approximately 7500 professionals around the world. Since 1986, engineers have been using Synopsys technology to successfully design and create billions of chips and systems. Founded by Dr Aart de Geus and a team of engineers from General Electric's Microelectronics Center, the company pioneered the commercial application of logic synthesis that has since been adopted by every major semiconductor design company. Without this technology, the complex designs of today would not be possible. With annual revenues of approximately $1.7billion, Synopsys offers a comprehensive, integrated portfolio of system level, IP, implementation, verification, manufacturing, optical and FPGA solutions that help address the key challenges facing designers. Its technology leading solutions help give customers a competitive edge in quickly bringing the best products to market while reducing costs and schedule risk.