Outlook 2012: Semiconductor IP

The implication for IP companies is that they need to be prepared to invest long term in those areas where their customers have come to rely on them as a supplier – and be able to sustain that investment. As IP becomes one more element of the already complex semiconductor supply chain, there is less and less room for tactical IP relationships. CONVERGING APPLICATIONS The consumer electronics market is hungry for devices that do 'everything' on one platform. To design the ICs at the heart of these devices, semiconductor companies need expertise in communications, computing and multimedia. Traditionally, these skill sets reside in separate businesses – very few companies have experts in all the domains required to design all elements of today's consumer driven, ultra converged SoCs from scratch. There are two ways to put the vast array of required functionalities onto a chip – either you design them or you reuse them. The fastest, lowest risk way is to reuse them; and you can do this either by using functionality that you've developed yourself or by buying third party IP. If you reuse internal IP, you have to address key issues such as who supports the IP? Who enhances it and/or maintains it? Are the features compatible with all of the application segments that you are targeting? The converged nature of today's consumer applications has accelerated the adoption of commercial IP and is fuelling the growth of the IP industry. GROWING COMPLEXITY The other aspect driving the increase in IP adoption is the complexity involved with keeping abreast of constantly changing standards and functionality. As chips get more complex, so too must the IP. You can't successfully bring a 100million gate chip to market by assembling blocks of 10,000 gates. To keep up with the complexity of designs, IP building blocks are getting bigger and more complex: as an example, USB 3.0 is roughly 20 times more complex to design and verify than USB 2.0. And just because an interface is difficult to design, it doesn't mean that it differentiates your design. A USB port is expected to work and to be interoperable with billions of existing USB products. Failure of a key interface like USB can cause multiple respins, savaging a device maker's profit margin. As IP blocks grow in functionality, we must think of them as complex subsystems, rather than simple hardware building blocks. In the same way that design teams looking to provide a specific function ask themselves 'What's the best mix of hardware and software I can provide in order to deliver the required performance, cost, power and lead time?', IP developers must ask a similar question 'What's needed to provide a solution to the customer's design requirements?'. Leading IP providers now provide a complete solution to a customer's needs – hardware IP, verification IP and software to speed time to market. To cope with the increasing functionality of devices and time to market pressures, companies are evolving their methodologies to accommodate growing SoC design complexity. To support the optimisation of function, power, area and schedule, chip designers are designing at higher levels of abstraction (such as the transaction level). Providing designers with transaction level IP models is crucial to help them model, analyse, understand and optimise SoC architectures. Similarly, fpga based and virtual prototypes of both the IP and the SoC enable faster time to market by allowing software development to start six to nine months earlier than traditional methods and to speed hardware/software integration and system validation. IP AS ENABLING TECHNOLOGY To better comprehend the difference IP has made when developing chips, one needs to look no further than processor IP. Today, it is relatively easy for an SoC design team to license a processor as IP, put it on their chip and, as a result, access a broad ecosystem of existing software. Not only that, it creates the opportunity to differentiate the chip in either software or with additional hardware. Providing access to software ecosystems is not the only way that IP enables innovation in the SoC space. The maturing of commercial third party IP has made it possible for semiconductor companies with great ideas to create very complex chips simply by licensing many of the required functions. Without access to high quality, third party IP, they may not have the expertise or engineering resources to realise their ideas in a marketable timeframe. On a similar theme, IP enables all design teams – whatever their size – to concentrate on their strengths. Used strategically, third party IP enables chip companies to focus on product differentiation. Without third party IP, semiconductor companies would have no choice but to dedicate valuable time and talent to simply recreate what has been done before. From a foundry perspective, IP has become a key enabler to shorten the time to production of chips designed in a new process technology. Historically, device models, logic libraries, embedded memories and standard I/Os were virtually all that early adopters of a new process needed. With the foundries' process enablement, chip designers could develop all digital functionality of their mostly digital chips and the limited amount of analogue/mixed signal functionality needed. With increasingly complex analogue/mixed signal functionality becoming part of today's advanced SoCs, the design of this functionality would have quickly become the dominant factor in the development schedule. To avoid this, foundries began working very closely with IP companies to ensure the availability of key analogue/mixed signal IP building blocks for their new process technologies. IP vendors must develop their analogue/mixed signal IP while the underlying process technology is still maturing and deliver it in time for the first tapeout to their mutual customers. In other words, foundry, semiconductor design house and IP vendor must partner closely to ensure the success of the first designs in new process technologies. FUTURE FOCUS Satisfying customers requires offering them the IP they want, meeting their feature requirements, having IP ready when they need it, and supporting them when they design it into the IC. If you can promise all of that, then how do customers select the best vendor? Customers have begun to realise how expensive 'cheap' IP can become. Making a poor quality IP block work can cost five times what you paid for it. The quality and dependability of the IP vendor is key; customers are looking for predictability and dependability and quality can never be high enough. The future trend is clear: designers are not only using bigger IP blocks, but also more of them. In addition to easing the integration of ever larger building blocks, the EDA industry must also make it easier to verify their correct interaction so they achieve the expected functionality quickly. It is imperative that the industry continues to develop innovative IP solutions that help SoC design teams shorten the time from concept to implementation and Synopsys is well positioned in this endeavour.